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Re: Scalability issues in the Internet routing system

  • From: Michael.Dillon
  • Date: Thu Oct 27 05:27:31 2005

> Another thing, it would be interesting to hear of any work on 
> breaking the "router code" into multiple threads.  Being able to 
> truly take advantage of multiple processors when receiving 2M updates 
> would be the cats pajamas.  Has anyone seen this?  I suppose MBGP 
> could be rather straightforward, as opposed to one big table, in a 
> multi-processor implementation.

Why bother multithreading when you can just use multiple
CPUs? :-)

Nowadays, a CPU is not a chip, it is a core. "Core" is
the name for a section of a chip which functions as
a CPU. Cores are actually software written in a language
such as VHDL (VHSIC Hardware Description Language). 
VHSIC stands for Very High Speed Integrated Circuit.
The core is "compiled" into hardware on either an 
FPGA (Field Programmable Gate Array) or an ASIC 
(Application Specific Integrated Circuit). An FPGA
can be reconfigured by software at any time, for instance
you could reprogram an FPGA to do route lookups for
a specific set of prefixes and change the hardware
whenever the prefix list changes.

Most ASICs nowadays are actually hybrid chips because
they contain an FPGA section. Now, back to cores. Since
the CPU core is simply software, it is possible to 
install multiple copies of the core on an FPGA or an
ASIC if there is enough space. The cores for RISC machines
like ARM are much smaller than the core for a Pentium
and therefore a simple RISC CPU core can be replicated
more times. 

Now, with that information in hand, you will be able
to understand just what Cisco and IBM have done in creating
the CRS-1 chip with a minimum of 188 CPUs on the chip.

Just as the line between routers and switches has become
blurred, so to has the line between hardware and software
become blurred.

--Michael Dillon